The present invention is directed to a novel chip carrier package and an improved method for interconnecting conductive layers in a chip carrier package.
With the advent of sophisticated equipment in the electrical and electronic fields, it has become necessary that the components of the various pieces of equipment conform to high standards which are set forth in the specifications of these components. For example, circuit boards which are used in relatively complicated pieces of equipment such as main frame computers, must be of a relatively high standard of quality in order to function in an efficient manner for a long period of time without deteriorating or breaking down, and thus causing an interruption in the function of the machine. This high quality of material and design is opposed to pieces of equipment requiring a lower standard of quality such as those used in personal computers, high quality television equipment, radios etc.
Circuit boards are prepared by laminating conducting sheets, e.g. copper sheets, with sheets of electrical insulating materials, such as glass fiber reinforced polyester resin sheets or nonreinforced polyimides. Such electrical circuit boards may be either rigid or flexible, and are further classified as single-sided (metal foil on one side of the insulating material only), double-sided (metal foil on both sides of the insulating material), or multilayered. Further for those circuit boards which are multilayered, the conductive layers within the package must be interconnected, for example with plated through holes as well as interconnected to other circuit boards or electrical components. Further still, there are multilayered circuit boards which contain a semiconductor chip, called chip carrier packages.
Current trends in the interconnect industry, especially for computer uses are moving toward higher signal, power and ground line densities, smaller size packages, and increased performance characteristics, such as less crosstalk, lower inductances, and greater resistance to failure from thermal cycling mechanical stress. These trends have placed greater demands upon design characteristics of multilayer interconnect packages such as chip carrier packages, and have made it more difficult to interconnect multiple conductive layers.
U.S. Pat. No. 4,517,050 discloses the method by which a conductive through-hole hole is formed through a dielectric sandwiched between conductors by forming a noncircular hole in a conductor, etching a hole through the dielectric and by deforming the conductor which has been undercut during the etching. This method does not permit for high dense packing of lines, as the holes formed in the conductive layer and the annular ring of conductor around such holes take up space needed for the circuit lines. This method can take up 22.5 mils on the conductive layer for interconnection purposes.
U.S. Pat. No. 3,969,815 discloses a process for providing electrical interconnection of two metal layers positioned on opposite sides of a substrate. A hole is initially drilled or bored completely through the two metal layers and the intermediate insulating layer. The hole in the insulating layer is enlarged by a selective etching process which only etches the insulating layer to form an enlarged annular hole in the insulating layer which undercuts the metal layer portions. Thereafter these overhanging metal portions on opposite sides of the insulating layer are deformed by pressure to contact or almost contact one another. The deformed metal portions are coated by galvanic metal which is overcoated by a thin layer, preferably tin, to form a conductive path. This process requires much tooling and set up work for the manufacture of the circuit board.